Design-Reuse

CCSDS 231.0-B-3 LDPC Encoder and Decoder IP Core from Creonic Now Available

Kaiserslautern, Germany, May 6, 2021 — Creonic GmbH, a leading IP core provider in the communications market, announced today the release of their new CCSDS 231.0-B-3 LDPC Encoder and Decoder IP cores ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...
Design-Reuse

LDPC (Low Density Parity Check) - A Better Coding Scheme for Wireless PHY Layers

R-Interface’s LDPC decoder platform provides to all Wireless and Wireline hardware designers an off-the shelf, full standard support, easy-to-integrate and proven solution for the Wimax Mobile ...
Total Telecom

AccelerComm’s New Highly Optimised LDPC Decoder in Software for Intel’s FlexRAN Reference Software Will Increase 5G Throughput by up to 3X

AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...