SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which ...
The open-source nature of RISC-V brings the benefits of a modular and royalty-free instruction set architecture (ISA) that eliminates licensing fees, can accelerate development, and fosters ...
The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
OXFORD, England--(BUSINESS WIRE)--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the delivery of its updated simulator for the RISC-V ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
A new technical paper titled “Test-driving RISC-V Vector hardware for HPC” was published by researchers at University of Edinburgh. “Whilst the RISC-V Vector extension (RVV) has been ratified, at the ...
A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that ...
One of the most interesting projects to watch these days in tech is RISC-V. The nonprofit organization and wider community is building an open-source and standardized instruction set architecture (ISA ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results