The AXI Protocol in a multi-master system design
1:38
The AXI Protocol in a multi-master system design
17.5K viewsFeb 14, 2020
YouTubeArm®
UVM for Verification Part 2 : Projects
UVM for Verification Part 2 : Projects
5.1K viewsJan 12, 2024
git.ir
UVM Basics: Block diagram of a Complete AXI Agent in UVM
6:09
UVM Basics: Block diagram of a Complete AXI Agent in UVM
5.5K viewsDec 9, 2019
YouTubeSystemverilog Academy
AXI PROTOCOL - 1
2:14:37
AXI PROTOCOL - 1
32.7K viewsApr 23, 2024
YouTubeMASTER VLSI
VLSI FOR ALL - AMBA Bus Architecture, AHB, APB and AXI Protocol.
41:54
VLSI FOR ALL - AMBA Bus Architecture, AHB, APB and AXI P…
54.6K viewsMay 2, 2021
YouTubeVLSI FOR ALL
What is UVM (Universal Verification Methodology)? | UVM TestBench Architecture
5:59
What is UVM (Universal Verification Methodology)? | UVM TestBench …
33.3K viewsFeb 17, 2022
YouTubeSemiconductor Club
Introduction to UVM | Design Verification using UVM | UVM Basics #uvm
4:57
Introduction to UVM | Design Verification using UVM | UVM Basi…
1.7K viewsFeb 2, 2024
YouTubeExplore VLSI
14:54
AXI Part1 : AMBA AXI Code Generation, Simulation, and Verifi…
1.1K viewsJan 13, 2025
YouTubeDesign with Manish
3:10
How To Integrate uvm_reg with AXI VIP | Synopsys
3.1K viewsMar 10, 2015
YouTubeSynopsys
25:22
UVM verification Code vs System Verilog verification Code | Comple…
1.8K viewsJan 26, 2025
YouTubeExplore VLSI
1:55:13
AXI PROTOCOL - 2
10.7K viewsApr 24, 2024
YouTubeMASTER VLSI
17:43
APB Protocol Verification Using UVM & SystemVerilog
500 views7 months ago
YouTubeChip Logic Studio
2:50
APB Protocol Verification Using UVM & SystemVerilog
664 views7 months ago
YouTubeChip Logic Studio
10:00
Introduction to UVM - The Universal Verification Methodology for Syst…
119.7K viewsMar 29, 2011
YouTubeDoulos Training
27:54
Easier UVM - Register Layer
46.1K viewsJun 29, 2016
YouTubeDoulos Training
3:32
How to Integrate AXI VIP into a UVM Testbench | Synopsys
19K viewsFeb 25, 2015
YouTubeSynopsys
30:11
Easier UVM - Configuration
29.6K viewsNov 5, 2015
YouTubeDoulos Training
24:28
Easier UVM - Components and Phases
22.3K viewsOct 29, 2015
YouTubeDoulos Training
25:36
TLM Connections in UVM
49.5K viewsNov 24, 2015
YouTubeDoulos Training
1:11:55
ZYNQ Training - Session 05 - Designing AXI Sub-systems Usin…
51K viewsMay 1, 2014
YouTubeMohammad S. Sadri
26:46
Easier UVM - Sequences
33.5K viewsApr 11, 2016
YouTubeDoulos Training
12:24
UVM Simplified (#10 UVM Interface and Connections)
21.9K viewsAug 27, 2020
YouTubeASIC Lab
33:46
UVM Built-in Methods | Universal Verification Methodology Tutorial
168 views3 months ago
YouTubeVLSI Simplified
24:01
First Steps with UVM Part 1
100.5K viewsMay 14, 2012
YouTubeDoulos Training
9:50
What is AXI Lite?
43.7K viewsApr 5, 2019
YouTubeDillon Huff
15:11
How the AXI-style ready/valid handshake works
12.6K viewsSep 1, 2022
YouTubeVHDLwhiz.com
9:55
UVM Introduction | Universal Verification Methodology 1
6K viewsApr 26, 2022
YouTubeVLSI Chaps
10:38
Master AXI protocol: AXI WRITE with FIXED ADDR and varying LE…
2.1K viewsMar 3, 2023
YouTubeVerifSudha
7:04
What is AXI (Part 1)
116K viewsApr 24, 2019
YouTubeDillon Huff
5:45
Master AXI protocol: AXI WRITE 1 Byte length
6K viewsMar 1, 2023
YouTubeVerifSudha
See more videos
Static thumbnail place holder